Fast Montgomery Modular Multiplier Using FPGAs
Francisco Pajuelo-Holguera, José M. Granado-Criado, Juan A. Gómez‐Pulido
Abstract
This letter details a fast and efficient implementation of the Montgomery modular multiplication by taking advantage of parallel multipliers and adders. This implementation was programmed in high-level synthesis language and tested on a field-programmable gate array device. In order to test the performance of the proposal, a sequential version of the algorithm was also implemented in hardware. Moreover, we compared the parallel implementation with a software version and with five contributions from the literature. This way, we found that our proposal improves the performance of all other implementations.
Topics & Concepts
Computer scienceField-programmable gate arrayModular designAdderMultiplier (economics)Modular arithmeticSoftwareParallel computingGate arrayComputer architectureImplementationEmbedded systemArithmeticComputer hardwareProgramming languageLatency (audio)MathematicsTelecommunicationsMacroeconomicsEconomicsCryptography and Residue ArithmeticCoding theory and cryptographyCryptography and Data Security