Oxide Channel Ferroelectric NAND Device with Source-Tied Covering Metal Structure: Wide Memory Window (14.3 V), Reliable Retention (> 10 Years) and Disturbance Immunity $(\Delta \mathrm{V}_{\text{th}}\leq 0.1\mathrm{V})$ for QLC Operation
Hongrae Joh, Giuk Kim, Jihye Ock, Seungyeob Kim, Sangmok Lee, Sangho Lee, Kwang-Soo Kim, Suhwan Lim, Jongho Woo, Wanki Kim, Daewon Ha, Jinho Ahn, Sanghun Jeon
Abstract
We show an oxide-channel (Ox. Ch.) based gate-injection type ferroelectric NAND (FeNAND) device with source-tied covering metal (SCM) and control dielectric (C.DE). The SCM and C.DE play crucial roles in the performance enhancement of FeNAND cells. (i) The proposed structure addresses the channel depletion issue of Ox.Ch. by utilizing accumulated holes in the grounded SCM during ERS. This increases the electric field across the gate interlayer and FE layer, thereby boosting ERS efficiency. (ii) The read operation of erase states distributes a significant portion of the read voltage to C.DE, intensifying the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{th},\text{ERS}}$</tex>. These effects result in a wide memory window (MW~14.3V). Furthermore, the introduction of a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{Si}_{3}\mathrm{N}_{4}$</tex> deep trap-level layer and careful gate stack design led to superior retention (MW:11.5V after 10 years) and disturbance immunity (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta \mathrm{V}_{\text{th}} < 0.1\mathrm{V}$</tex> after <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10^{5}$</tex> disturb cycles). We also verify the roles of SCM and C.DE through analytical modeling. Lastly, the proposed structure is compatible with current 3D-NAND fabrication, offering equivalent channel hole pitch and density.