FPGA Implementation of Memristor Emulators Using Fractional Order Calculus: A High-Precision Reconfigurable Approach
Bo Xu, Hang Geng, Leping Jiang, Songting Zou, Kai Chen, Zhen Liu
Abstract
Fractional order memory elements (FOMEs), which exhibit marked memory and nonlinear characteristics, have found broad utilization across an array of interdisciplinary fields. Unfortunately, a significant impediment to their integration into engineering applications is the scarcity of commercially available nanomaterial-based FOMEs. In this paper, we propose a hardware architecture with high FPGA resource utilization efficiency based on the Grünwald–Letnikov approximation and sampling theorem. This architecture can simultaneously realize three fractional calculus (FC) algorithms: the fixed window length (FWL), K-piecewise linear function ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> PLF), and FWL& <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> PLF without modifying the FPGA binary file. The method proposed in this paper has lower resource consumption, fewer memory requirements, and higher computational performance, resulting in lower step length by 106 and higher operating frequencies compared with existing methods. Moreover, we design an FC experimental platform based on a digital oscilloscope that is capable of realizing FOMEs of any order by modifying parameters. In addition, a universal digital circuit of FOMEs is designed in FPGA, which helps to directly display signals at both ends of FOMEs in the digital domain, avoiding interference from circuit noises. Hardware experiments and digital simulations show that the proposed FPGA-based FOMEs hardware circuit method has high precision and reconfigurability, which further accelerates the engineering application of FOMEs.