A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer
Dongsuk Kang, Jae-Woo Park, Injae Park, Minsu Park, Xuefan Jin, Kyu‐Dong Hwang, Daehan Kwon, Jung‐Hoon Chun
Abstract
In this article, we propose a duobinary transceiver for graphics double-data-rate (GDDR) memory interfaces. The proposed voltage-mode driver complies with the GDDR impedance specifications without sacrificing the ratio of level mismatch (RLM). The quarter-rate time-interleaved successive approximation duobinary receiver (Rx) reduces the forwarded clock frequency and minimizes the capacitive loading of the front-end analog equalizer (EQ). To compensate for the channel loss, the transmitter is composed of a three-tap feed-forward EQ, and the Rx employs a continuous-time linear EQ. Also, an EQ adaptation scheme applicable to duobinary signaling is proposed. The transceiver achieves a 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> bit error rate at 21 Gb/s with 1.42 mW/Gb.