A 50–112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS
Xuqiang Zheng, Hao Ding, Feng Zhao, Danyu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
Abstract
This article presents a 50–112-Gb/s current-mode four-level pulse amplitude modulation (PAM-4) transmitter with a two-tap fractional-spaced feed-forward equalizer (FFE). The principle analysis shows that the fractional-spaced FFE can provide an extended compensation range beyond the Nyquist frequency without amplifying noise. For the transmitter prototype implementation, the tap delay is adjusted by a coarse–fine capacitor array-based delay cell located in the quarter-rate clock path. Dynamic latches, pseudo-AND2s, and bandwidth-enhanced 4:1 multiplexers are employed to guarantee an adequate timing margin and a sufficient bandwidth for the data rate of 112 Gb/s. A linearity-optimized FFE driver is employed to overcome the current compression caused by the channel-length modulation. Fabricated in a 65-nm CMOS process, the measurement results show that the proposed fractional-spaced FFE can significantly improve the eye-opening in terms of expanding the eye width and optimizing the eyelid thickness. The PAM-4 transmitter can operate in both full-rate PAM-4 and half-rate NRZ modes, achieving a maximum data rate of 112 Gb/s with an energy efficiency of 2.17 pJ/bit.