A Scalable FPGA Engine for Parallel Acceleration of Singular Value Decomposition
Yu Wang, Jeong-Jun Lee, Yu Ding, Peng Li
Abstract
Singular value decomposition (SVD) is a fundamental computational kernel and tool wildly used in data analytics such as least squares regression, principle components analysis (PCA), and pattern recognition. While a number of dedicated hardware processors have been proposed to accelerate the computationally intensive SVD computation, these designs suffer from poor flexibly and scalability, and/or lack full consideration of compute and data movement challenges associated with SVD. This paper presents a scalable parallel SVD FPGA engine based on the Hestenes-Jacobi method. We propose a so-called Maximum Data Sharing (MDS) ordering, which maximizes on-chip data reuse, and significantly reduces the expensive off-chip data movements and bandwidth requirement. Our SVD engine can flexibly decompose rectangular matrices with variable sizes and speed up SVD computation by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$80\mathrm{X}$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$300\mathrm{X}$</tex> when compared with software SVD solvers such as the Eigen package running on high-performance CPUs. It can process much larger matrices than the previously reported FPGA designs.