A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier
H CHANG, Tung‐Cheng Lin, Tai‐Cheng Lee
Abstract
A pipelined SAR ADC is proposed to achieve faster conversion by employing residue conversion and partial bit conversion in parallel to lessen timing constraints. Additionally, a varactor-based dynamic amplifier is adopted to improve linearity for a 10-b accuracy. The single-channel ADC achieves 1 GS/s with a peak SNDR 41.37 dB at a Nyquist input and consumes 9.4 mW.
Topics & Concepts
Successive approximation ADCEffective number of bitsLinearityAmplifierVaricapComputer scienceElectronic engineeringResidue (chemistry)Electrical engineeringChemistryComparatorVoltageEngineeringBandwidth (computing)CMOSElectrodeCapacitanceTelecommunicationsBiochemistryPhysical chemistryAnalog and Mixed-Signal Circuit DesignAdvancements in Semiconductor Devices and Circuit DesignLow-power high-performance VLSI design