Comparison of Short Circuit Failure Modes in SiC Planar MOSFETs, SiC Trench MOSFETs and SiC Cascode JFETs
Erfan Bashar, Ruizhu Wu, S.N. Agbo, Simon Mendy, Saeed Jahdi, Jose-Ortiz Gonzalez, Olayiwola Alatise
Abstract
In this paper, a comprehensive comparative analysis is performed on the short circuit (SC) withstand time and failure modes between a 650 V SiC Planar MOSFET, a 650 V SiC Trench MOSFET and a 650 V SiC Cascode JFET. The short circuit tests have been performed at a DC link voltage of 400 V with gate turn-OFF voltages at 0 V and -5 V. The results show that the SiC Cascode JFET failed in a source-to-drain short circuit with the gate still capable of blocking voltage while the SiC Planar and Trench MOSFETs failed with the Gate-Source (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</inf> ) terminal short circuited and Drain-Source (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> ) terminals still capable of blocking voltage. Furthermore, short circuit withstand times measured on the SiC Planar and Trench MOSFETs showed an increase (20% for the Planar MOSFET and 9% for the Trench MOSFET) when the device gate voltages were turned-OFF with -5V compared to 0V. This was due to the increased inductance of the negative voltage gate driver reducing the peak short circuit current. In the case of the SiC Cascode JFET, there was no dependence of the short-circuit withstand time on the V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</inf> turn-OFF voltage.