Improved Immunity to Sub-Cycling Induced Instability for Triple-Level Cell Ferroelectric FET Memory by Depositing HfZrOₓ on NH₃ Plasma-Treated Si
Hao‐Kai Peng, Chia-Ming Liu, Yu‐Cheng Kao, Pin‐Jiun Wu, Yung‐Hsien Wu
Abstract
Split-up effect caused by sub-cycling would change the coercive voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\textrm {C}}$ </tex-math></inline-formula> ) of a ferroelectric HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> (HZO) film by the induced local internal field due to oxygen vacancy (Vo) related behaviors and is detrimental to MLC operation. By depositing the HZO on NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> plasma-treated Si, due to the high-quality SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> interfacial layer that reduces the amount of Vo in the HZO, the ferroelectric FET (FeFET) memory reveals a large memory window of 3.2 V by +6/-5 V with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5 {\mu } \text{s}$ </tex-math></inline-formula> pulse width and much improved reliability against sub-cycling for multi-level cell (MLC, 2 bits/cell) operation than those without plasma treatment. The FeFET memory also for the first time displays the stable (threshold voltage) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\textrm {TH}}$ </tex-math></inline-formula> for each state for triple-level cell (TLC, 3 bits/cell) operation up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times 10^{\textrm {3}}$ </tex-math></inline-formula> cycles that meets the industry requirement under strict sub-cycling and exhibiting quadruple-level cell (QLC, 4 bits/cell) operation with desirable retention, ushering in new paradigms for advanced high-density memory applications.