A 56-GHz Fractional-N PLL With 110-fs Jitter
Yu Zhao, Onur Memioglu, Long Kong, Behzad Razavi
Abstract
A fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loop (PLL) architecture incorporates a switched-current finite impulse response (FIR) filter to suppress the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula> ) noise. Using a compact, low-power divide-by-8 circuit and realized in 28-nm CMOS technology, the PLL exhibits a phase noise of −98 dBc/Hz at 1-MHz offset in the fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> mode while consuming 23 mW and occupying an active area of 0.1 mm 2.