3D Stacked Devices and MOL Innovations for Post-Nanosheet CMOS Scaling
Naoto Horiguchi, Hans Mertens, T. Chiarella, S. Demuynck, V. Vega-Gonzalez, A. Vandooren, A. Veloso, M. Garcia Bardon, Giuliano Sisto, Anshul Gupta, Zsolt Tökei, S. Biesemans, Julien Ryckaert
Abstract
3D stacked devices without area penalty from device-device space, such as complementary FET (CFET), is promising for post-nanosheet CMOS scaling. New MOL architectures, such as backside power delivery network (BSPDN) or Vertical-Horizontal-Vertical routing style, are required to connect 3D stacked devices without wiring congestions and resistance increase. Process/material innovations are necessary to enable high aspect ratio and 3D integration in CFET integration with new MOL architectures.
Topics & Concepts
NanosheetCMOSScalingRouting (electronic design automation)Materials scienceElectronic engineeringProcess (computing)OptoelectronicsComputer scienceNanotechnologyEngineeringMathematicsGeometryOperating system3D IC and TSV technologiesSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit Design