Compact Quadratic Boost Switched-Capacitor Inverter
Jagabar Sathik Mohamed Ali, Marif Daula Siddique, N. Sandeep, Arpan Hota, Dhafer Almakhles, Saad Mekhilef, Udaykumar R. Yaragatti
Abstract
This article presents a new topology for a single-stage nine-level (9L) switched-capacitor inverter. The structure of the proposed topology is not only simple but also compact. The proposed topology is developed with self-voltage balancing and a low number of power components. The output voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v<sub>o</sub></i> ) gain is four times higher than the input voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> ). Each mode of operation is discussed with a detailed current path. The conventional sinusoidal pulsewidth modulation technique is used to generate the gate pulses. Next, the experimental results are obtained from a 1 kW prototype setup. The proposed topology is tested under different scenarios such as load change, input voltage changes, and modulation variations. Both simulation and experimental results have good agreement in terms of efficiency. Finally, a detailed comparative study is performed with other recent 9L inverters to prove the merits of the proposed topology.