Dual-Mechanism Memory Combining Charge Trapping and Polarization Switching for Wide Memory Window Flash Cell

Abstract

We propose a novel memory device to overcome the limited <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> window in charge trap flash (CTF) memory, which prevents the realization of a high number of bits/cell. The proposed memory device (named “dual-mechanism memory”) has a ferroelectric HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layer on the channel so that the conductance of the channel can be controlled by the remanent polarization ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {r}}{)}$ </tex-math></inline-formula> . In addition, since trap-rich Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">{3}</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">{4}</sub> and tunnel SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> layers are located on top of the ferroelectric layer, the conductance of the channel can also be controlled by electron injection/removal from/to the gate electrode. Compared to a reference memory that uses only charge trapping, the dual-mechanism memory provided up to 96% wider memory window and exceeded the theoretical limit of ISPP slope in a conventional CTF. It also showed up to 36% improvement in retention characteristics. The enhanced retention performance is attributed to compensation of the E-field stress by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\text {r}}$ </tex-math></inline-formula> .

Topics & Concepts