An Efficient Sorting Algorithm for Capacitor Voltage Balance of Modular Multilevel Converter With Space Vector Pulsewidth Modulation
M. Aswini Kumar, Jayanta Biswas, Mukti Barai
Abstract
Thisarticle presents an efficient analogue sorting algorithm for balancing the submodule (SM) capacitor voltages of modular multilevel converter (MMC). The proposed analogue sorting algorithm offers the advantage of fast convergence rate without any need of recursive loops for the implementation on embedded devices. It can be easily implemented with combinational logic operations on field programmable gate array (FPGA) and provides less hardware and computational overhead. The functionality and performance of the proposed analogue sorting algorithm is evaluated with the simulation model of three phase five-level MMC in MATLAB/Simulink environment. The real time implementation of the proposed sorting algorithm with the SM capacitor voltage balancing strategy is implemented on Altera/Cylone - I (EP1C12Q240C8N) FPGA. A five-level continuous space vector pulsewidth modulation (CSVPWM) is realized on a PIC microcontroller (PIC18F452). A down-scaled model of single-phase five-level MMC is designed and constructed to investigate the reliable and stable operation of MMC with the proposed analogue sorting algorithm and SVPWM method. Simulation and experimental results are presented for validation.