A Transformer-Based Series-Resonance CMOS VCO
Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Zhihua Wang, Baoyong Chi
Abstract
The LC parallel tank is widely used in oscillators, and its noise optimization techniques are relatively mature. However, there has always been a bottleneck in phase noise (PN) performance, and the multi-core technique can only improve it partially. This article proposes a brand-new oscillator structure leveraging a transformer-based series tank, which can tolerate larger currents, generate greater oscillation amplitudes, and achieve significant PN suppression. A general active circuit for series-resonance (SR) is analyzed. The proposed series tank provides adjustable low input impedance, is well-suited for high-frequency operation, and suppresses parasitic modes. With the folded transformer, the layout implementation is simplified. An SR voltage-controlled oscillator (VCO) prototype is designed and fabricated using a 65-nm CMOS process. It achieves a measured PN of −132.1 dBc/Hz at a 1-MHz offset and a corresponding figure of merit (FoM) of 187.4 dBc/Hz at a 10.65-GHz carrier frequency. The SR VCO is applied to a phase-locked loop (PLL), which achieves 33.7 fs of jitter with a 100-MHz reference clock, significantly reducing the demands on the reference path.