D-Band × 8 Frequency Multiplier Using Complementary Differential Frequency Doubler
Jae‐Hyun Park, Dong-Yeol Yang, Kyu-Jin Choi, Byung‐Sung Kim
Abstract
A D-band <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 8$ </tex-math></inline-formula> frequency multiplier is presented in this letter. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 8$ </tex-math></inline-formula> frequency multiplier consists of two stages of the newly proposed common load complementary push-push doublers (CL-CPPDs) and one stage of NMOS push-push doubler. The proposed CL-CPPD uses a single load to generate a balanced output with high harmonic rejection (HR) and can be easily cascaded using transformers for a high multiplication ratio with low dc power consumption. The chip is fabricated by using a 40-nm CMOS technology, and it achieves a maximum output power of −2.48 dBm with an input power of 0 dBm in the frequency range of 131.2–144.8 GHz. All HRs are over 34 dBc in the frequency range of 131.2–144.8 GHz. The total dc power dissipation is 41.4 mW when supplied from a single voltage of 0.9 V and occupies 0.37 mm2 of the chip area.