An error efficient and low complexity approximate multi‐bit adder for image processing applications

Abstract

Summary Approximate computing‐based hardware is directed towards reduction in area and power consumption; it finds better suitability in various image processing applications. In order to achieve low complexity, approximate techniques are applied in the arithmetic units which provide promising results in enhancing the performance of DSP processors with optimal degradation on its accuracy. In this paper, two approximate full adder designs are proposed, namely, the first design as proposed approximate full adder 1 ( P A A 1 ) and the second design as proposed approximate full adder 2 ( P A A 2 ). In both the designs, the approximation on the Boolean expressions is carried out to reduce the hardware complexity with the significant tolerance on the error rate. Also, a multi‐bit approximate carry select adder is proposed with the utilization of P A A 1 and P A A 2 , respectively. The performance of the proposed adders is analyzed in terms of parameters like gate count, structural synthesis, error, and also in terms of image metrics. The proposed and existing designs are synthesized using Synopsys Design Compiler with TSMC 65 nm technology for better comparison. Synthesis results indicate that the proposed 16‐bit approximate carry select adder (CSLA) shows a significant reduction of 58% in area delay product and 70% in power delay product, in comparison with the conventional CSLA. The image metrics results also validate that the proposed adder with highest peak signal‐to‐noise ratio is highly adoptable for image processing applications.

Topics & Concepts