An Eight-Element 140 GHz Wafer-Scale Phased-Array Transmitter with 32 dBm Peak EIRP and > 16 Gbps 16QAM and 64QAM Operation
Siwei Li, Zhe Zhang, Bhaskara Rupakula, Gabriel M. Rebeiz
Abstract
This paper presents an 8-element 140 GHz wafer-scale phased-array transmitter in CMOS. It is based on intermediate-frequency (IF) beamforming transmit channels with 5-bit phase and 4-bit gain control at the IF band (9–14 GHz) with LC-based Wilkinson combiners, a shared local-oscillator (LO) multiplier chain and distribution network. On-chip image rejection filters (IRF) and LO leakage cancellation circuits are designed in each channel to improve the array in-band linearity and suppress the LO leakage. Differential on-chip antenna feeds (on top metal) are electromagnetically (EM) coupled to high-efficiency patch antennas on a 100-µm-thick quartz superstrate. The antennas are placed λ/2 (~140 GHz) apart between adjacent channels in the horizontal and vertical directions with a chip size of 5.4 mm × 5.1 mm. The 4 × 2-element array can scan to ±30° in the elevation plane (E-plane). The phased-array transmitter results in a measured EIRP of 27–32 dBm at 134–146 GHz. It supports up to 16 Gb/s data rate per carrier for both 16 and 64QAM waveforms at an EIRP of 22 and 20 dBm, repectively, with −25 dBc EVM (for 64QAM). To the best of our knowledge, this paper presents the first CMOS wafer-scale phased-array transmitter at 140 GHz, resulting in high radiated power and high speed communications.