9.7 A 94.3dB SNDR 184dB FoMs 4<sup>th</sup>-Order Noise-Shaping SAR ADC with Dynamic-Amplifier-Assisted Cascaded Integrator
Kai-Cheng Cheng, Soon-Jyh Chang, Chung-Chieh Chen, Shuo-Hong Hung
Abstract
The noise-shaping (NS) SAR ADC, which features the advantages of sigma-delta ADCs and SAR ADCs, is high accuracy and low power, so it stands out as a great choice for audio applications of IoT devices. Attaining high-performance and high-yield in an NS-SAR ADC is challenging due to the requirements of meeting a high-order noise transfer function (NTF), power efficiency, and robustness across PVT variations at the same time. The error-feedback (EF) structure implements FIR filters with multi-cycle delays [1], which simplifies implementation but makes NTF coefficients sensitive to gain variation. Therefore, foreground trimming is necessary for precise amplifier gains. The cascaded-integrator-feedforward (CIFF) structure [2–5] implements cascaded integrators to realize NTF, whose coefficients are less sensitive to variation. Closed-loop amplifier-based integration can achieve a nearly perfect NTF, but the high-gain amplifier with multiple stages may introduce extra noise or large power consumption [2]. Passive charge-sharing integration is implemented to reduce power consumption, but it leads to a mild NTF and requires larger capacitors for noise suppression. Capacitor-stacking with dynamic buffers/amps can be used to achieve a nearly perfect NTF [3–4], but it requires N buffers/amps to implement an Nth-order NS, making it less power efficient.