A Low-Power 1-V Supply Dynamic Comparator
Subhash Chevella, Daniel O’Hare, Ivan O’Connell
Abstract
This letter presents a low-power dynamic comparator for ultralow power applications. The prototype is designed in a 65-nm CMOS process with a supply voltage of 1 V and is compared against the widely used double tail latch comparator in terms of power consumption and input referred rms noise. The addition of cross-coupled devices to the input differential pair prevents the comparator internal nodes from fully discharging to ground in contrast to the conventional architecture. This reduces the power consumption while achieving similar noise levels. Measurements demonstrate that the proposed comparator achieves an input referred rms noise voltage of 220 μV against 210 μV for the conventional comparator with a 30% reduction in power. The proposed circuit consumes 0.19-pJ energy per comparison.