Insight into gate dielectric reliability and stability of SiO <sub>2</sub> /GaN MOS devices
Yuhei Wada, Mikito Nozaki, Takuji Hosoi, Takayoshi Shimura, Heiji Watanabe
Abstract
Abstract Gate dielectric reliability and stability of SiO 2 /GaN metal–oxide–semiconductor (MOS) capacitors were systematically investigated by means of area-dependent and time-dependent dielectric breakdown (TDDB) characteristics. It was found that, although high-temperature post-deposition annealing (PDA) that causes Ga diffusion in SiO 2 gate dielectrics has only a minor impact on electrical properties of the SiO 2 /GaN interfaces, PDA at temperatures above 800 °C severely degrades dielectric reliability and stability of GaN MOS devices. Area dependences of time-zero and TDDB characteristics revealed the formation of local weak spots and generation of uniform charge trapping sites throughout the gate oxides depending on the PDA temperatures. Determinant factors for dielectric reliability of SiO 2 /GaN gate stacks and reasonable measures for improving their reliability and stability are discussed on the basis of the experimental findings.