A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC
Hongzhi Zhao, Minglei Zhang, Yan Zhu, Rui P. Martins, Chi‐Hang Chan
Abstract
This article presents a high-speed 5-bit/cycle successive-approximation register (SAR) analog-to-digital converter (ADC) facilitated by a linearized configurable voltage-to-time (V2T) buffer with time-domain (TD) quantization. Configuring the TD full-scale (TD-FS) input of the TD quantizer among cycles allows a single capacitive digital-to-analog converter (CDAC). The configuration is accomplished by the V2T buffer, which also provides isolation between the backend TD quantizer and CDAC, thus enabling over 3-GHz effective resolution bandwidth. The configurated FS also relieves the critical accuracy requirement in the TD quantizer due to the small residue voltage in the backend cycles, while the two-stage compensation scheme suppresses the nonlinearity from the V2T buffer. By incorporating 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> time interleaving, the 28-nm prototype achieves a 2.8-GS/s sampling rate with a 51.79-dB signal-to-noise and distortion ratio (SNDR) and 72.36-dB spurious-free dynamic range (SFDR) at a Nyquist input while consuming only 18 mW under a 0.9-V supply, resulting in a Walden figure of merit (FoM) of 20.3 fJ/conversion-step.