Ferroelectric and Interlayer Co-optimization with In-depth Analysis for High Endurance FeFET
Yuejia Zhou, Zhongxin Liang, Wenpu Luo, Ming Yu, Runteng Zhu, Xiao Lv, Jiachen Li, Qianqian Huang, Fei Liu, Kechao Tang, Ru Huang
Abstract
In face of the critical endurance issue, for the first time we take a holistic perspective to co-optimize the ferroelectric materials and interlayer in FeFET. Compared to the common HZO based gate stack, the novel combination of Hf <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.95</inf> Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.05</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> +Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> enhances the endurance to $\gt 5 \times 10 ^{9}$ cycles while maintaining a retention > 10 years. In-depth analysis based on DFT and DQSCV reveal the reduction of interlayer electric field and interface charge trapping as the mechanism of optimization. We also develop a distributed interface trap model to correlate different trapping dynamics with the interlayer property in each device. This work pushes forward the understanding and development of high endurance strategy for FeFET.