Self-Aligned E-Mode GaN <i>p</i>-Channel FinFET With ION > 100 mA/mm and ION/IOFF > 10⁷
Nadim Chowdhury, Qingyun Xie, Tomás Palacios
Abstract
This letter demonstrates self-aligned <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -channel FinFETs based on a GaN-on-Si wafer. While the self-aligned gate process helps to achieve shortest possible source-to-drain distance to compensate for low hole mobility in GaN (~20 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> ), the FinFET-architecture provides strong electrostatic control over the channel. Our fabricated transistors with 40 nm fin width, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{SD}=120$ </tex-math></inline-formula> nm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{G}=90$ </tex-math></inline-formula> nm exhibits an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\text{ON}} \approx 140$ </tex-math></inline-formula> mA/mm, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\text{ON}}/\text{I}_{\text{OFF}}>10^{7}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{TH}=1$ </tex-math></inline-formula> V, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$SS=150$ </tex-math></inline-formula> mV/dec, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m,max}=14$ </tex-math></inline-formula> mS/mm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{\text{ON}}=61\,\,\Omega \cdot $ </tex-math></inline-formula> mm. By precisely controlling the recess depth, enhancement-mode (E-mode) operation was also achieved. Our best E-mode device shows an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\text{ON}} \approx 125$ </tex-math></inline-formula> mA/mm, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\text{ON}}/\text{I}_{\text{OFF}}>10^{7}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{TH}=-0.3$ </tex-math></inline-formula> V, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{\text{ON}}=69\,\,\Omega \cdot $ </tex-math></inline-formula> mm. In addition, record low subthreshold swing of 80 mV/dec for devices with fin width of 40 nm and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{SD}=240$ </tex-math></inline-formula> nm attests to the strong gate control over the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -channel achieved by the FinFET-architecture.