A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ
Daewoong Lee, Jaehyeok Baek, Hye-Jung Kwon, Daehyun Kwon, Chulhee Cho, Sang-Hoon Kim, Donggun An, Chulsoon Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye‐Ran Kim, Sun-Young Park, Hyoung-Joo Kim, Hoseok Seol, Juhwan Kim, Jung-Bum Shin, Gil-Young Kang, Yong-Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, Chan Yong Lee, Seungseob Lee, Tae‐Hoon Park, Chi Sung Oh, Hyodong Ban, Hyung-Jong Ko, Hoyoung Song, Tae-Young Oh, Sangjoon Hwang, Kyung-Suk Oh, Jung-Hwan Choi, Joo‐Young Lee
Abstract
This article introduces a 16-Gb T-coil-based graphics double-data-rate 6 (GDDR6) dynamic random access memory (DRAM) with merged-multiplexer (MUX) transmitter (TX), optimized data clock (WCK) operation to enhance I/O bandwidth. T-coil is implemented for the first time in a DRAM process. Moreover, an alternative-data-bus (ADB) is employed to solve the frequency limit of the data bus. The proposed T-coil-based GDDR6 DRAM achieves 27 Gb/s/pin with 1.35 V in a DRAM process.