A 256 Kbit Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub>-based FeRAM Chip with Scaled Film Thickness (sub-8nm), Low Thermal Budget (350<sup>o</sup>C), 100% Initial Chip Yield, Low Power Consumption (0.7 pJ/bit at 2V write voltage), and Prominent Endurance (>10<sup>12</sup>)
Pengfei Jiang, Haijun Jiang, Yang Yang, Lu Tai, Wei Wei, Tiancheng Gong, Yuan Wang, Xu Pan, Shuxian Lv, Boping Wang, Jianfeng Gao, Junfeng Li, Jun Luo, Jianguo Yang, Qing Luo, Ming Liu
Abstract
In this work, we successfully resolve the remanent polarization (P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</inf> ) degradation issue, which is caused by the thermal budget decreasing and the film thickness scaling of Hf <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</inf> Zr <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> (HZO), and co-integrate the TiN/HZO/TiN capacitors with large initial P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</inf> and low operating voltage in the Back-End-of -Line (BEOL) of 130nm CMOS technology to provide a 256 Kbit 1T1C FeRAM chip. Firstly, we prove that the P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</inf> degradation is caused by the increasing component of anti-ferroelectric (AFE) phase. Then, utilizing the pre-crystallization engineering and O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> treatment to the TiN bottom electrode (BE), not only the formation of t-phase is effectively suppressed, but also the required annealing temperature is reduced. The enhancement of ferroelectricity is related to the small thermal expansion of TiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> interface layer, which can induce large tensile stress to HZO during the annealing process. Moreover, the oxidization of TiN BE can prevent it absorbing oxygen from HZO, and the reduced oxygen vacancy (Vo) defects can improve both the retention and TDDB characteristics. Based on the above optimizations, the chip demonstrates 100% initial chip yield, >150mV sense margin after 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> write cycles, power consumption of 0.7 pJ/bit at 2V write voltage, over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> endurance and 10 years retention.