Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch
Jaehyun Park, Juhun Park, Kyu‐Man Hwang, Jinchan Yun, Dahye Kim, Sung-Il Park, Jejune Park, Jinwook Yang, Jae Won Jeong, Chuljin Yun, Jinho Bae, Sam Park, Daihong Huh, Sanghyeon Kim, Seungeun Baek, Suk Yang, Inhae Zoh, Jung-Han Lee, T.I. Kim, Younsu Ha, Sunjung Lee, S.W. Park, Bong Jin Kuh, Daewon Ha, Sangjin Hyun, Su Jin Ahn, Jaihyuk Song
Abstract
In this study, we have demonstrated 3-Dimensional Stacked FET (3DSFET) with Self-Aligned Direct Back-side Contact (SA-DBC) and Back-side Gate Contact (BGC) in 48nm gate pitch, which is the smallest dimension and the world's first demonstration reported so far. Simultaneous threshold voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{t})$</tex> targeting for both n- and pFET in common gate and n/p-connection with vertical common contact were also verified in addition to our previous report [1]. As a result, we believe that the most of key components for ultimate cell height scaling of 3DSFET has been verified to continue the logic technology scaling beyond 1nm node.