A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology
Bo Zhang, Anand Vasani, Ashutosh Kumar Sinha, Alireza Nilchi, Haitao Tong, Lakshmi Rao, Karapet Khanoyan, Hamid Hatamkhani, Xiaochen Yang, Xin Meng, Alexander Wong, Jun Kim, Ping Jing, Yehui Sun, Ali Nazemi, Dean Liu, Anthony Brewster, Jun Cao, Afshin Momtaz
Abstract
This article presents a power- and area-efficient multistandard serial link transceiver designed for application rates of up to 112 Gb/s, such as OIF CEI-112G and IEEE 802.3ck 400GBASE. The receiver features a continuous time linear equalizer, a programmable gain amplifier (PGA), a three-tap sampling-based feed-forward equalizer, and an 18-tap decision feedback equalizer. The transmitter uses a half-rate 2:1 multiplexer (MUX) with a duty cycle distortion corrected clock and a 7-bit digital to analog converter (DAC)-based driver with a six-tap feed-forward equalizer. The shared phase-locked loop (PLL) has a tuning range of 40–60 GHz with 0.12-ps rms jitter in integer mode and 0.16-ps jitter in fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> mode measured at 56 GHz. The transmitter shows an eye with an RLM of 0.999. The transceiver can compensate for up to 43.9-dB insertion loss (IL) channel at 112 Gb/s. It consumes 690-mW per receiver (RX)/transmitter (TX). It is fabricated in 7-nm FinFET technology and occupies 0.63-mm2 per RX/TX.