Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications
Aibin Yan, Zhengzheng Fan, Liang Ding, Jie Cui, Zhengfeng Huang, Qijun Wang, Hao Zheng, Patrick Girard, Xiaoqing Wen
Abstract
With the reduction of technology nodes now reaching 2 nm, circuits become increasingly susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU), single-event-transient (SET), double-node-upset (DNU), and even triple-node-upset (TNU), must be considered for safety-critical applications. This article first presents four advanced circuit components (i.e., advanced voters), that have very small overhead compared with the traditional voters. The proposed Advanced Triple-Modular-Redundancy (ATMR) and Advanced Quadruple-Modular-Redundancy (AQMR) voters only consist of four and six inverters, respectively, to provide effective tolerance against SNUs and DNUs. To further filter SETs, a Schmitt-trigger (ST) instead of an inverter at the output-level is used to construct the ATMR-ST and AQMR-ST voters. These proposed voters can also be extended to tolerate TNUs. Next, these voters are used for latch hardening, so that this article also presents a series of voter-based latch designs, to ensure high reliability with cost-effectiveness. Simulation results demonstrate the node-upset tolerance and/or SET-filterability of the proposed voters and voter-based latches, respectively. Simulation results also demonstrate that the proposed ATMR voter can reduce delay, power, and area by 55.2, 32.8, and 32.2%, respectively, compared with the traditional TMR voter; the proposed so-called high-impedance state-insensitive, TNU-tolerant, and SET-filterable latch can reduce delay, power, and area by 78.9, 15.8, and 28.6%, respectively, compared with the state-of-the-art TNU hardened latch.