SiN/in-situ-GaON Staggered Gate Stack on p-GaN for Enhanced Stability in Buried-Channel GaN p-FETs
Li Zhang, Zheyang Zheng, Yan Cheng, Yat Hon Ng, Sirui Feng, Wenjie Song, Tao Chen, Kevin J. Chen
Abstract
GaN-based complementary logic (CL) integrated circuits (ICs) for the prospective power integration have been demonstrated on the commercial p-GaN gate power HEMT (high-electron-mobility transistor) platform. This work reports a delicately designed gate structure featuring a SiNx/in-situ-GaOxN <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</inf> staggered gate stack on GaN p-channel field-effect transistors ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$p$</tex> -FETs) for stability enhancement. The threshold voltage of GaN p-FETs with such a novel gate stack is barely changed within wide ranges of negative and positive voltage bias and temperature, which thereby enables the implementation of stable GaN CL ICs. The optimized monolithic GaN CL inverters and ring oscillators preserve decent performances and exhibit high stability over long-period operations and across a temperature range from 25 °C to 400 °C. As such, it becomes much more feasible for energy-efficient GaN-based CL functional blocks to be integrated into GaN power ICs.