Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs
Gokul Krishnan, Sumit K. Mandal, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao
Abstract
State-of-the-art in-memory computing (IMC) architectures employ an array of homogeneous tiles and severely underutilize processing elements (PEs). In this article, the authors propose an area and energy optimization methodology to generate a heterogeneous IMC architecture coupled with an optimized Network-on-Chip (NoC) for deep neural network (DNN) acceleration. -Yiran Chen, Duke University.
Topics & Concepts
AccelerationInterconnectionHomogeneousComputer scienceEnergy (signal processing)ArchitectureEfficient energy useState (computer science)Computer architectureArtificial neural networkEmbedded systemParallel computingEngineeringArtificial intelligenceElectrical engineeringTelecommunicationsAlgorithmMathematicsPhysicsStatisticsArtVisual artsClassical mechanicsCombinatoricsAdvanced Memory and Neural ComputingFerroelectric and Negative Capacitance DevicesSemiconductor materials and devices