Investigation of Failure Mechanisms of 1200 V Rated Trench SiC MOSFETs Under Repetitive Avalanche Stress
Xiaochuan Deng, Wei Huang, Xu Li, Xuan Li, Chao Chen, Yi Wen, Jiawei Ding, Wanjun Chen, Yongkui Sun, Bo Zhang
Abstract
In this article, the repetitive avalanche ruggedness of silicon carbide metal–oxide–semiconductor field-effect transistors (MOSFETs) with asymmetric trench (AT) and double trench (DT) structure is investigated experimentally. The different failure mechanisms, i.e., thermal-induced fatigue or field oxide breakdown for AT-MOSFET and electric field induced gate oxide degradation or breakdown for DT-MOSFET, are verified by device decapsulation and TCAD simulation. Different from the transient failure in single-pulse avalanche test, the degradation and failure under repetitive avalanche stress are related to the accumulation of gate oxide traps or thermal stress. Under high energy ratio condition, DT-MOSFET fails with shorted gate-drain terminal after only 2k unclamped inductive switching (UIS) cycles. Microscopic failure analysis shows an obvious crack through the bottom gate oxide to N-drift layer, whereas the electrical parameters of AT-MOSFET remain stable during 12k UIS cycles until gate leakage current of 10 mA exceeds the failure threshold of devices. The thermal-induced field oxide breakdown is found upon polysilicon gate in AT-MOSFET. Under low energy ratio condition, over 5% reduction of threshold voltage and <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state resistance is observed in DT-MOSFET due to hot holes injection in gate oxide. However, the threshold voltage of AT-MOSFET is almost constant and an approximately 10% increase of <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state resistance caused by thermal fatigue is observed.