A Three-Level Boost Converter With Fully State-Based Phase Selection Technique for High-Speed V<sub>CF</sub> Calibration and Smooth Mode Transition
S. H. Lee, Yeon-Woo Jeong, Se-Un Shin
Abstract
In this article, a three-level current-mode boost converter with a fully state-based phase selection (FSPS) technique is presented. The proposed FSPS technique selects the operation phase adaptively to ensure the voltage across the flying capacitor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {CF}}$ </tex-math></inline-formula> ) to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{O}$ </tex-math></inline-formula> /2 and changes the operation mode of a three-level boost converter (3L-BST). It enables the flying capacitor to be charged or discharged consecutively at the same duties every switching period and the operation mode to be changed smoothly. Therefore, 3L-BST improves the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {CF}}$ </tex-math></inline-formula> calibration speed with the stable startup and removes the sub-harmonic oscillation of the inductor current caused by the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {CF}}$ </tex-math></inline-formula> calibration, and the output voltage fluctuation is alleviated in the mode transition region. In addition, to compensate the stability of both valley and peak current-mode control for a wide output voltage range, the proposed FSPS technique adopts the adaptive slope generator (ASG) of which the slope can be changed from negative to positive. This work, fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> bipolar-CMOS-DMOS (BCD) process, occupies an area of 5.51 mm2. The peak efficiency of the proposed 3L-BST is 95.3%, with an input range of 2–6 V, an output range of 5–32 V, and a 0.5-A maximum load current. The inductor current ripples are <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.45\times $ </tex-math></inline-formula> smaller than prior <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {CF}}$ </tex-math></inline-formula> calibration techniques. The total startup time is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$490~\mu \text{s}$ </tex-math></inline-formula> .