First Demonstration of Monolithic CFET Inverter at 48nm Gate Pitch Toward Future Logic Technology Scaling
Siyong Liao, L. Yang, Wei-Xiang You, Ting Wu, Y. C. Lee, T.K. Chiu, Jung‐Lung Hsu, W.D. Ho, Yucheng Yang, Mi‐Ching Tsai, Hao-Hsiu Hung, Robert F. Chen, Yaohua Li, Shuhua Huang, C.Y. Lee, K.F. Yang, K. K. Hu, Yung‐Hsiao Chiang, Hung-Ping Lo, Stacy Ho, Chenyan Sha, Jia‐Yao Jhang, Guang-Cheng Wang, Cheng‐Yi Liu, Wei‐Yen Woon, Chun-Yeon Lin, S.H. Chen, Kai‐Chien Yang, Jiajun Wen, Chia‐Ming Chang, Yi Shen, Peihua Lin, Cheng‐Chen Yang, Wei Yip Loh, G. Tsai, C.H. Chen, Bing‐Hung Chen, Min Cao
Abstract
This study presents the first functional advanced CFET inverter with an industry-leading 48nm gate pitch, exhibiting well-balanced voltage transfer characteristics up to 1.2 V. In this paper, we elaborate on the advancements in our nanosheet-based monolithic complementary field-effect transistor (mCFET) process architecture, which builds upon our previous work. Key developments include a vertical dipole patterning process for independent n/p threshold voltage tuning, a vertical metallized drain local interconnect for n/p epitaxy connection at the common drain, and backside middle-of-line contacts and interconnects that improve performance and increase design flexibility. A comprehensive evaluation of the electrical performance of the mCFET devices with different configurations validates the effectiveness of our integrated process architecture. The successful demonstration of fully operational mCFET inverters marks an important milestone in the pioneering of CFET technology, paving the way for future logic technology scaling and the advancement of power, performance, area, and cost (PPAC).