Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS
Komala Krishna, Nandakumar Nambath
Abstract
Dynamic comparators are the core of high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. Most of the dynamic comparators attain high-speed operation only for sufficiently high input difference voltages. The comparators’ performance degrades at small input difference voltages due to a limited preamplifier gain, which is undesirable for high-speed, high-resolution ADCs. To overcome this drawback, a cascode cross-coupled dynamic comparator is proposed. The comparator improves the differential gain of the preamplifier and reduces the common-mode voltage seen by the latch, which leads to a much faster regeneration at small input difference voltages. The proposed comparator is designed, simulated, and compared with the state-of-the-art techniques in a 65 nm CMOS technology. The results show that the proposed comparator achieves a delay of 46.5 ps at 1 mV input difference, and a supply of 1.1 V.