Litcius/Paper detail

Graphene Capping of Cu Back-End-of-Line Interconnects Reduces Resistance and Improves Electromigration Lifetime

Keun Wook Shin, Yeonchoo Cho, Seung‐Geol Nam, Alum Jung, Eun‐Kyu Lee, Chang‐Seok Lee, Min‐Hyun Lee, Hyeon‐Jin Shin, Kyung‐Eun Byun

2023ACS Applied Nano Materials13 citationsDOI

Abstract

As the pitch size of Cu lines in the back-end-of-line (BEOL) is decreased below a few tens of nanometers, resistivity exponentially increases and electromigration (EM) causes device failure. Graphene has shown promise for both problems, but graphene grown at 400 °C for the BEOL-compatible process is far from its ideal honeycomb lattice. In this report, we successfully demonstrated that graphene grown at low temperatures improves Cu resistance by 5% and increased the EM lifetime by 78 times compared to Cu-only interconnect. We proved that the resistivity gain by graphene capping is due to the improvement of the Cu surface, excluding other effects of parallel resistivity and grain boundary scattering. First-principles calculation demonstrated that the graphene edge–Cu bond can inhibit the migration of Cu vacancies, thereby improving the EM lifetime. We manipulated the graphene nanostructure to have more edge contact with Cu, which enhanced the EM lifetime by 116 times compared to Cu-only interconnect. This work systematically investigated the causes for the decrease in resistance of graphene-capped Cu and discovered key factors that contribute the improvement of the interconnect reliability.

Topics & Concepts

GrapheneElectromigrationMaterials scienceElectrical resistivity and conductivityGrain boundaryBack end of lineEnhanced Data Rates for GSM EvolutionOptoelectronicsInterconnectionContact resistanceElectrical resistance and conductanceSheet resistanceNanotechnologyComposite materialElectrical engineeringMicrostructureComputer networkLayer (electronics)DielectricComputer scienceEngineeringTelecommunicationsCopper Interconnects and ReliabilitySemiconductor materials and devicesSemiconductor materials and interfaces