Fault-Tolerant Core Mapping for NoC based architectures with improved Performance and Energy Efficiency
B. Naresh Kumar Reddy, Alex Pappachen James, Aruru Sai Kumar
Abstract
Due to the rapid growth of the components encapsulated on the On-chip architecture, the performance degradation and communication issues between the cores has a significant impact on NoC architecture. Thus, ensuring an implementation of a mapping algorithm which is resilient to the faults occurring in an application could mainly resolve the communication and performance issues. This research paper introduces an effective algorithm named as FTMAP (Fault tolerant mapping algorithm), that exemplifies the core mapping on the basis of selected task graph, and replaces the faulty cores with the available free core termed as core replacement. This implementation focuses predominantly on the replacement of the faulty cores and assessing the communication energy of the network by utilizing it on different benchmarks. The trial results show that it decreases the correspondence energy by 7.2%, 11.4%, 13.6% regarding NFT, 1FT, 2FT when contrasted with FTTG and 5.4%, 8.2%, 9.8% concerning NFT, 1FT, 2FT when contrasted with K-FTTG.