A Compact Model for BEOL-Compatible Ferroelectric Thin Film Transistors With Metal/Ferroelectric/Semiconductor Structure
Wei Zhang, Jianze Wang, Chen Sun, Qiwen Kong, Zhen Wu, Xiao Gong, Xuanyao Fong
Abstract
In this article, we investigate the dynamic response of BEOL-compatible ferroelectric thin film transistors with amorphous oxide semiconductor channel (OS-FeTFTs) using a physics-based compact model. Our modeling methodology is based on the nucleation-limited-switching (NLS) model to capture the dynamics of multi-domain ferroelectric (FE) switching, as well as the multiple-trapping-releasing (MTR) mobility model to capture the trap-limited conduction (TLC) mechanism in amorphous oxide semiconductor channel. Conservation of FE polarization charge and network charge in the semiconductor channel are calculated self-consistently in the HSPICE circuit simulator for metal/ferroelectric/semiconductor (MFS) gate stack structure. Our proposed model elucidates two different switching mechanism in OS-FeTFTs determined by the sequence of polarization switching and depleted holes due to different flat band voltage. Furthermore, memory window (MW) is enhanced due to the successful polarization switching with different sweeping time and voltage range. Meanwhile, the write and read operation of OS-FeTFTs array is also introduced and simulated, showing large sense margin (SM) for memory applications. The relationship between the critical erase voltage and FE thickness are studied to provide design rules for future BEOL-compatible memory device operation.