17.8 A 170MHz-Lock-In-Range and −253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator

Younghyun Lim, Juyeop Kim, Yongwoo Jo, Jooeun Bang, Seyeon Yoo, Hangi Park, Heein Yoon, Jaehyouk Choi

202017 citationsDOI

Abstract

This work presents a 12-to-14.5GHz SSPLL, robust to frequency disturbances with a wide lock -in range. The proposed f D -correcting loop (FCL) generates a new signal of S us with unevenly spaced edges that are adaptively aligned with the zero crossing points of the output signal of the SSPLL, S our (top right of Fig. 17.8.1). Since S us can detect the f D of S OUT more frequently, the lock-in range can be extended. Meanwhile, in the main loop, the original reference clock, S REF , senses the jitter of S OUT as it does conventionally. Consequently, since the role of S us is limited to the detection of f D events, S us has a relaxed requirement of the jitter, thus requiring only 104W. The FCL monitors S our seamlessly, so f D can be detected quickly, decreasing the TRA. Since the positions of the edges of S us are realigned adaptively according to the muitiplication factor, M, the resolution of f out in the SSPLL can be maintained as f REF .

Topics & Concepts

JitterComputer scienceAlgorithmTopology (electrical circuits)Electrical engineeringEngineeringTelecommunicationsAdvancements in PLL and VCO TechnologiesPhotonic and Optical DevicesRadio Frequency Integrated Circuit Design

17.8 A 170MHz-Lock-In-Range and −253dB-FoM<sub>jitter</sub> 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator

Abstract

Topics & Concepts