Understanding the Memory Window of Ferroelectric FET and Demonstration of 4.8-V Memory Window With 20-nm HfO<sub>2</sub>
Yixin Qin, Zijian Zhao, Suhwan Lim, Kijoon Kim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Kai Ni
Abstract
In this work, with the goal of developing a large memory window (MW) ferroelectric field-effect transistor (FeFET) for high-density stand-alone storage applications, we provide a deep look into the MW of a FeFET and clarify the definition on the MW through combined theoretical and experimental studies. We show that the following hold: 1) conventionally thought maximum MW of a FeFET (i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2{E} {_{\text {C}}} {t} {_{\text {FE}}}$ </tex-math></inline-formula>) is accurate only for dc sweep and may not be accurate for pulsed memory operation as it neglects the contribution from other layers in the gate-stack; 2) for intrinsic FeFET operation that only depends on polarization switching, adding a dielectric layer into a FeFET gate-stack at best keeps the same MW as the one without the dielectric layer if assuming the same polarization is switched in both cases or worse as most likely less polarization can be switched; 3) by integrating FeFETs with or without a top dielectric Al2O3 layer, we demonstrate from experiment that adding a dielectric layer reduces the MW; and 4) with a 20-nm-thick HfO2, a large MW of 4.8 V is demonstrated, which can accommodate tightly distributed multilevel cell (MLC) and triple-level cell (TLC), showing the potential of FeFET as high-density storage technology.