Area Optimization of CMOS Full Adder Design Using 3T XOR
Somashekhar Malipatil, Vikas Maheshwari, Marepally Bhanu Chandra
Abstract
GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This technique allows minimization of area and power consumption of digital circuits. In this design XOR gate is designed using 3 transistors and CMOS full adder is designed based on two 3T XOR and one 2T Mux. Using 8 transistors the full adder is designed in this paper and voltage scaling also done by reducing supply voltage. In this proposed full adder, the power consumption 4.604μW is achieved and the total area is 144μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
Topics & Concepts
AdderXOR gateCMOSMultiplexerComputer scienceTransistorElectronic circuitElectronic engineeringPower consumptionLogic gateMinificationSerial binary adderElectrical engineeringPower (physics)VoltageEngineeringPhysicsMultiplexingProgramming languageQuantum mechanicsLow-power high-performance VLSI designAdvancements in Semiconductor Devices and Circuit DesignAnalog and Mixed-Signal Circuit Design