High-Voltage a-IGZO TFTs With the Stair Gate-Dielectric Structure
Guangan Yang, Mengyao Li, Zuoxu Yu, Yong Xu, Huabin Sun, Siyang Liu, Weifeng Sun, Wangran Wu
Abstract
In this work, a high-voltage amorphous In-Ga-Zn-O (a-IGZO) thin-film-transistors (TFTs) with the stair gate-dielectric at the drain side were demonstrated. The electrical properties of the proposed TFTs were comprehensively investigated. The breakdown voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> ) was significantly enhanced, and the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> of over 60 V is achieved in the TFT with the stair length ( L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stair</sub> ) of 3 μm. The TCAD simulation and emission microscope (EMMI) measurements are performed to reveal the working and breakdown mechanisms of the proposed stair gate-dielectric TFTs. The descending electron current density in the channel lowers the stair-gate TFTs' ON-current. Meanwhile, the stair-gate-dielectric region endures a strong electric field and improves the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> of the device. Finally, the exponential trade-off relationship between the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> and the ON-state resistance ( R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) was established.