Fault Tolerant Reversible Full Adder Design Using Gate Diffusion Input

Abstract

GDI technique allows minimization of area and power consumption of digital circuits. The reversible gate preserves same parity between output and input vectors is called fault tolerant but the dimension should be 3. In this design, Peres Gate is designed using Gate Diffusion Input using 8 transistors. The proposed new Peres Gate is used to design full adder with power efficient and fault tolerant. In this work power consumption 51.62μW is achieved for supply voltage 1V and the total area is 492μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The schematic is designed in DSCH 2 and layout is done in Microwind 2.

Topics & Concepts