Super Split-Gate LDMOS With Optimized R<sub>SP</sub> and 79.5% Q<sub>GD</sub> Decrease on 55-nm BCD Platform for High-Frequency xPU Power Supply
Dingxiang Ma, Ming Qiao, Yangjie Liao, Yixun Jiang, Jiawei Wang, Zhaoji Li, Bo Zhang
Abstract
In this article, the super split-gate LDMOS (SSG LDMOS) on 55-nm BCD platform is proposed to overcome the tradeoff relationship among breakdown voltage (BV), specific ON-resistance (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>SP</roman></sub>), and gate-to-drain charge (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>GD</roman></sub>), while satisfying the requirement of high-frequency power system-on-chip (PwrSoC) applications. This device has an ultrashort Gate1 to reach an extremely low <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>GD</roman></sub> and a biased Gate2 to achieve low <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>SP</roman></sub>. Measured data confirm an optimal tradeoff between <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>SP</roman></sub> and BV for 7–16-V low-voltage device. Significantly, compared with conventional low-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>GD</roman></sub> LDMOS, dynamic performances of 16-V SSG LDMOS show substantial improvements, including a 79.5% reduction in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>GD</roman></sub> (0.186 nC/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sup>) in dc domain and obvious decreases of 89.1% and 71.4% in gate-to-drain capacitance for 0-and 16-V drain voltage, respectively, in the ac domain. These improvements directly benefit high-current dc–dc converter performance. Employing BSIM4-modeled SSG LDMOS, the simulation demonstrates that the efficiency of 89.2% (at 24 A) is achieved for a 5-MHz <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>in</roman></sub> 12–<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>out</roman></sub> 1.8 converter. Furthermore, the measured switching figure of merit (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>SP</roman></sub>⋅<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>GD</roman></sub>) implies a significant superiority of SSG LDMOS over reported discrete devices and existing BCD technology.