A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS
Athanasios T. Ramkaj, Juan Carlos Pena Ramos, Marcel Pelgrom, Michiel Steyaert, Marian Verhelst, Filip Tavernier
Abstract
This article presents a 5-GS/s 12-b passive-sampling 8×-interleaved hybrid analog-to-digital converter (ADC) that achieves a low-frequency SFDR/SNDR of 75.2/62.4 dB and a Nyquist SFDR/SNDR of 65.4/58.5 dB. A significant power reduction while attaining a bandwidth in excess of 6 GHz and a high spectral purity are enabled by: 1) an on-chip terminated very fast settling buffer-less input front end; 2) an on-chip clock chain with as low as 11-fs added jitter; 3) an asynchronous three-stage pipelined-successive approximation register (SAR) sub-ADC; and 4) on-chip co-designed analog-digital calibrations deal with sub-ADC and time-interleaving (TI) artifacts to achieve the desired spectral performance levels. The 28-nm bulk CMOS prototype chip occupies a total area of 4.56 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a core area of 1.76 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 158.6 mW from a 1-V supply, leading to the Nyquist figure of merits of Schreier (FoMS) and Walden (FoMW) of 160.5 dB and 46.1 fJ/conversion step, respectively.