Complementary Oxide Semiconductor-Based 2T0C DRAM Macro with CFET Peripherals Using TeO<sub>x</sub>-PFET/IGZO-NFET for 3D Memory Integration
Yuanzhe Su, Tianbo Liu, Jianshi Tang, Yang Li, Rui An, Yingchao Du, Zijian Tang, Yong Zhang, Yong Fan, Yifan He, Man Shi, Haoyan Yang, Tianyu Huang, J. Zhang, Ziyue Zhu, Gang Wang, Chao Zhao, Cong Wang, Lujun Pan, P. Yao, Dong Wu, Bin Gao, Hao Qian, Hui Wu
Abstract
To meet the increasing demand for on-chip memory to handle high-bandwidth data transfer, we present the first fully integrated complementary oxide semiconductor (OS)-based 2T0C DRAM macro with complementary field-effect transistor (CFET) peripherals. This was accomplished using top-gate tellurium suboxide PFET (TeO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf>-PFET) and back-gate InGaZnO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> NFET (IGZO-NFET) via an ultra-low-temperature (≤150 °C) backend-of-the-line (BEOL) process. By integrating IGZO- NFET as the write transistor and TeO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> PFET as the read transistor, a 4×4 array of hybrid-polarity 2TOC DRAM cells was demonstrated, achieving 2-bit/cell capacity and a decent retention. In addition, the proper functionality of the peripherals based on OS-based CFET was validated by electrical measurements. This work presents a viable DRAM macro for future 3D memory integration.