A Novel SiC MOSFET With Embedded Auto-Adjust JFET With Improved Short Circuit Performance
Xu Li, Xiaochuan Deng, Xuan Li, Xiaojie Xu, Yi Wen, Hao Wu, Wanjun Chen, Bo Zhang
Abstract
In this letter, a novel planar gate SiC MOSFET with embedded auto-adjust normally-on JFET (ADJ-MOSFET) is proposed and characterized to improve short circuit capability. The normally-on auto-adjust JFET (AD-JFET) is embedded in P-well region as the conduction path of electrons from N-type source to the channel region of SiC MOSFET. Meanwhile, the P-type source of device splits into two parts, one of which serves as the gate of AD-JFET. Under high DC bus voltage (short circuit) conditions, the effective channel width of AD-JFET will be reduced by the increased depletion charge. Therefore, the potential barrier of AD-JFET channel will increase rapidly, making it difficult for electrons transporting. The potential barrier of AD-JFET will be adjusted by that of the JFET region in drift region automatically, resulting in a reduction of the saturation (peak short circuit) current caused by the higher potential barrier of SiC MOSFET. Compared with conventional planar gate SiC MOSFET, ADJ-MOSFET not only reduces 33% peak short circuit current, but also increases short circuit withstanding time from <inline-formula> <tex-math notation="LaTeX">$8~\mu \text{s}$ </tex-math></inline-formula> to 14 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> under 800 V DC bus voltage. Furthermore, an auto-adjust JFET barrier model is proposed for SiC ADJ-MOSFET.