The Future of Design for Test and Silicon Lifecycle Management
Janusz Rajski, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer
Abstract
A GROWING NUMBER of safety-critical and mission-critical applications require extremely reliable operations. In automotive electronics and hyperscale data centers, the ever-increasing demands for exceptionally high quality will push for solutions relying largely on manufacturing design for test (DFT) throughout the entire silicon lifecycle, including in-system and in-field operations. Advanced technology nodes, especially those at 7 nm and below with 3D multi-die packaging, observe new complex parametric defects and reliability risks related to aging. Cloud service providers have reported silent data corruption errors caused by subtle IC defects producing faulty results only occasionally what makes them extremally difficult to find [1], [2]. A closer examination of the problem reveals underlying issues [3]: test escapes due to marginalities as well as latent or aging defects, early-life failures, random defectivity, and environmental conditions that lead to malfunctions.