A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR
Min Chen, Yutong Zhao, Nuo Xu, Fan Ye, Junyan Ren
Abstract
Recently, the neural network has been applied to calibrate the successive-approximation-register and pipelined analog-to-digital converters (SAR-Pipelined ADCs), which requires no prior knowledge. However, the large hardware area of the full-precision neural network (FPNN) limits the promotion of this method. This paper proposes an optimization scheme called partially binarized and fixed neural network (PBFNN) to simplify the hardware through the following mechanisms. First, the multipliers that occupy a considerable area are optimized by binarization. Second, the fixed layer does not require training, hence saving the hardware for backpropagation. A 14-bit 60 MS/s ADC prototyped in 28-nm CMOS process is used to verify the PBFNN-based calibration. The measurement results show that the ADC achieves an SFDR of 95.0 dB and an ENOB of 10.6 bit. Compared with the previous scheme, the SFDR and ENOB are lossless. We also synthesize both schemes in Synopsys Design Compiler with a 28-nm library. The synthesis result indicates that the hardware area is optimized by 71.95%.