A Novel Cascadable TCAM Using RRAM and Current Race Scheme for High-Speed Energy-Efficient Applications
Kangqiang Pan, Amr M. S. Tosson, Ningxuan Wang, Y. Zhou, Lan Wei
Abstract
In this work, a novel ternary content addressable memory (TCAM) design is proposed using resistive random-access memory (RRAM) array in 2T2R configuration. The suggested memory array adopts the current-race (CR) sensing mechanism incorporated with a match-line (ML) booster in the sensing amplifier (SA) to improve energy efficiency, search speed and tolerance to RRAM switching variation. Several innovations are implemented to enhance the design further. For large TCAM arrays, match-line sensing amplifier (MLSA) direct cascading (DC) and an SR-latch cascading (SRC) schemes are proposed and compared in search speed, energy efficiency and MLSA noise margin. A same clock phase cascading (SCPC) scheme is also introduced to reduce latency in cascading structure by placing evaluation phase of all stages in the same clock phase. Furthermore, an RRAM-based tunable delay element (RRAM-TDE) is used in the TCAM design to provide flexibility and robustness against RRAM switching variation. The resulting system demonstrates excellent speed, energy and area efficiency against other TCAM designs using CMOS and emerging non-volatile memory (eNVM). To the best of our knowledge, the proposed 64-bit 1-stage TCAM system's speed and energy consumption match the best performance reported by other eNVM-based TCAM designs. The proposed design on a 128-bit 2-stage system also has speed and energy consumption comparable to SRAM-based TCAMs with the extra advantages of (a) compact size (90% reduction) and (b) non-volatility.